Design Techniques for Mash Continuous-Time Delta-Sigma Modulators by Qiyuan Liu Alexander Edward Carlos Briseno-Vidrios & Jose Silva-Martinez

Author:Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios & Jose Silva-Martinez
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

OA1 design parameters are also annotated in Fig. 6.2 as an example. The bandwidth of each stage is numerically optimized to provide a high gain up to the modulator bandwidth of 50 MHz while maintaining a good phase margin . Additional NMOS capacitors are added to the first- and the second-stage outputs to achieve the low bandwidth required for an optimal frequency response while maintaining a low noise performance. Their nonlinearity is not a concern due to the small signal swings they experience. On the other hand, the third stage directly drives the parasitic input capacitance of the fourth stage to save power consumption. The inputs, the outputs, and the internal voltages V 1−3 of the OA can be shorted by switches to reset the modulator.

Figure 6.3 shows the transconductor G m1 schematic used in the OA. The input transistors M 1 are cascoded by the transistors M 2 to achieve a high gain, a high transconductance efficiency, and low input capacitances using small channel length transistors. Cascoding is not used for the load transistors M 3 as their large channel length provides a sufficiently high output resistance, and their headroom needs to be large for a low-noise operation. Self-biased common-mode feedback (CMFB) is implemented by the resistors R 1 and the capacitors C 1. The current source I b2 is added to raise the transconductor output common-mode voltage. The transconductors G m2 and G m12 have an identical schematic to that of the transconductor G m1, whereas the transconductors G m3 and G m13 have a slightly different schematic to that of the transconductor G m1, in which the current source I b2 is not used.

Fig. 6.3Transconductor G m1 schematic used in the OA

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